FPGAs may be used to implement large systems that include millions of gates and megabits of embedded memory. Of the tasks required in managing and optimizing a design, placement of components on the FPGAs and routing connections between components on the FPGA utilizing available resources can be the most challenging and time consuming. In order to satisfy placement and timing specifications, several iterations are often required to determine how components are to be placed on the target device and which routing resources to allocate to the components. The complexity of large systems often requires the use of EDA tools to manage and optimize their design onto physical target devices. Automated placement and routing algorithms in EDA tools perform the time consuming task of placement and routing of components onto physical devices.
Traditional duplication procedures performed after placement identified sufficiently long and critical connections between nodes or components in a system. For each connection identified, a determination would be made as to whether duplicating the source of the connection and placing it closer to its destination would improve the overall slack of the system. Although these procedures yielded some positive results, the procedures failed to recognize situations where duplication of a group of components would be beneficial when duplication of a single component in the group alone would not be beneficial.
Thus, what is needed is a method and apparatus for performing compound on on FPGAs.